1. Field of the Invention
The present invention relates to drive circuitry in television and video display monitors, more particularly to drive circuitry for EHT (electrical high tension) and scan output stages in multiscan displays.
2. State of the Art
In television and video display monitors using a CRT (cathode ray tube), a horizontal deflection current is produced in a horizontal deflection coil to create a magnetic field used to deflect an electron beam (produced by a cathode of the CRT) back and forth across a display screen. As the electron beam is scanned back and forth across the display screen, it is modulated to produce on the display screen spots of varying luminous intensity, thus forming an image to be viewed. A high voltage, referred to as EHT (electrical high tension), is applied to an anode of the CRT and accelerates the electron beam, causing it to strike the screen at a very high speed.
Typically, a periodic horizontal drive signal is applied to a horizontal scan output stage (i.e., a power transistor) to produce a train of high-voltage retrace pulses used to generate the horizontal retrace current. The same train of retrace voltage pulses may also be used to generate the EHT using a voltage step-up transformer, commonly referred to as the flyback transformer. Where high performance is not required, as in television sets and some less-expensive video monitors, a single output stage is used to generate the horizontal retrace current and to generate the EHT, with the flyback transformer and the retrace coil being combined on a common core as part of a single assembly. In high performance video monitors, separate scan and EHT output stages are provided, with the retrace coil and the flyback transformer also being separated. Power is provided to the scan and EHT output stages from a so-called B+ power supply.
In a multiscan monitor, the horizontal drive frequency can vary between, say, 30 kHz and 80 kHz. At lower horizontal frequencies, current builds up in the primary of the flyback transformer for a longer period of time while the EHT output stage is turned on. When the EHT output stage is turned off, therefore, a larger voltage pulse is generated than in the case of a higher horizontal frequency. If the power supply to the EHT output stage were to remain the same throughout the range of possible horizontal frequencies, the EHT would then be frequency dependent, resulting in performance variations.
Furthermore, even in the case of a single horizontal frequency, variations in picture content and consequent variations in beam current may also produce variations in the EHT. For example, the top half of a picture frame might be black (no beam current) and the bottom half of the picture frame might be white (high beam current). During high beam current, the EHT is loaded down and reduced, for example by 1-2 kV. As a result, the picture becomes wider in the white are than in the black area, creating picture distortion. Therefore, it is common for the B+ power supply to the EHT output stage to be varied using a step-down power supply and a control loop in order to maintain a fairly constant EHT.
In addition, in order to maintain the correct horizontal deflection current across a range of frequencies, it is common to provide a separate B+ supply for the scan output stage and to vary the same using a step-down power supply and a control loop.
Further details concerning the regulation of independent B+ power supplies for scan and EHT output stages using pulse width modulation may be found in U.S. application Ser. No. 08/505,424 (Attorney Docket Number P1597/253) filed on even date herewith and incorporated herein by reference.
The board range of frequencies possible in a multiscan display also affects the drive circuit of the scan output stage. Referring to FIG. 1, in a known drive circuit for a scan output stage, a bipolar transistor or other amplifying 12 is coupled to a load 19, comprising in this example, a diode 20, a storage capacitor 22 and a horizontal deflection yoke coil 24 connected to a DC power supply via a terminal 26. The coil 24, diode 20 and capacitor 22 form a resonant load.
An input 18 of the transistor 12 is driven from a DC power supply terminal 28 through a rapidly acting switch 30 and a driver circuit 13. The switch 30 opens and closes at the desired horizontal scan frequency. The driver circuit 13 includes a transformer 32 having a primary winding 34 and a secondary winding 36. A coil 38 is connected between one end of the transformer secondary 36 and the transistor input 18. The other end of the transformer secondary is coupled to a common terminal 40 through a diode 42. A resistor 44 may be provided between the transistor input 18 and the common terminal 40, which is also tied to the emitter 14 of the transistor 12. Furthermore, a resistor 46 may be provided between the switch 30 and the reference terminal 40.
Waveform traces of the transistor input current (I.sub.b), transistor output current (I.sub.c) and transistor output voltage (V.sub.ce) are illustrated in FIG. 2. In FIG. 2, the waveforms are not drawn to scale. Referring to FIG. 1 and FIG. 2, in operation, when the switch 30 closes, a current 50 (FIG. 1) flows through the transformer primary 34 to the transistor input 18. The switch 30 remains closed for an interval 52 in FIG. 2 during which the input current I.sub.b increases approximately linearly as shown in the upper trace of FIG. 2 (left side). There is a corresponding increase in the output current 53 (FIG. 1), shown as I.sub.c in the middle trace of FIG. 2. The input current I.sub.b and the output current I.sub.c are related. For convenience of future reference, the input current I.sub.b flowing during the interval 52 is referred to as the forward input current I.sub.bf and identified as current 50 in FIG. 1 and I.sub.bf in FIG. 2. The portion of the output current I.sub.c (current 53 in FIG. 1 ) which corresponds to I.sub.bf is identified in FIG. 2 as I.sub.cf. During this interval, the transistor output voltage, measured between terminals 14 and 16 and denoted V.sub.ce for convenience as and shown as the lower trace in FIG. 2, has a small value denoted as V.sub.fl corresponding to the saturated forward voltage drop of the transistor.
At the end of interval 52, I.sub.b will have risen to its peak forward value (e.g., I.sub.bfp .congruent.1.5A). The switch 30 then opens and the collapsing magnetization in the windings of the transformer 32 cause an immediate reversal of the input current I.sub.b so that a current 54 in FIG. 1 now flows out of the transistor input 18 through the inductor 38, the transformer secondary 36 and the diode 42 and back to the reference terminals 14, 40. The current 54, referred to as the reverse input current, continues to flow during the interval 56 (FIG. 2), and is denoted in FIG. 2 as I.sub.br. The interval 56 is typically shorter than the interval 52 and the reverse current 54 is larger than the peak forward current (e.g., I.sub.br .congruent.4-5A). Since the transistor 12 has not yet turned off, the output current I.sub.c continues to flow in the same direction as previously and may, as shown in FIG. 2, even continue to increase for a time after has been reversed. The abrupt reversal of input current I.sub.b is a feature of the drive circuit 13.
The interval 56 is referred to in the art as the device storage time and corresponds approximately to the time that is required to extract from the transistor 12 the excess charge stored therein during the interval 52 by the input current I.sub.bf. In the case of a bipolar transistor, this excess charge is the base charge which places the transistor in saturated forward conduction. During the first part of the interval 56, the output voltage has a small but slightly increased value denoted as V.sub.ft (typically about 2V). The transistor output current 53 (I.sub.c) continues to increase until substantially all of the stored charge has been removed from the transistor 12, at which point the transistor output current 53 drops from its peak value I.sub.cp (typically about 7A) toward zero and V.sub.ce rapidly rises. Because of the resonant nature of the load formed by the coil 24, diode 20 and capacitor 22, the waveform during the first part 59 of the final interval 58 is substantially a half sine wave having a peak value denoted as V.sub.ceor. (typically about 1000V). This is the maximum reverse voltage that the transistor must block. During this transition interval from conduction to blocking when both I.sub.c and V.sub.ce have values different than zero a substantial amount of transient energy is being dissipated within the transistor 12.
Once the peak blocking voltage V.sub.ceor. has passed, V.sub.ce swings negative. This negative going V.sub.ce excursion (e.g., V.sub.rl .congruent.-8V to -20V). during the second part 60 of the interval 58 occurs because of the finite amount of time required for the diode 20 to turn on. Once the diode 20 turns on, V.sub.ce is damped during the third part 61 of the interval 58 at the diode forward drop (e.g., V.sub.r2 .congruent.0.7V). At the end of the interval 58, the switch 30 closes again and the cycle is repeated.
In FIG. 2, the lower part of the V.sub.ce waveform has been expanded so that small voltage changes occurring during certain part of the cycle may be clearly seen despite the presence of peak V.sub.ce values (e.g., V.sub.ceor) that are 10.sup.3 -10.sup.4 times larger.
The transient power dissipation during transistor turn-off is very sensitive to the amount of stored charge and hence to the amount of input drive which produced the stored charge during the forward conduction portion of the cycle. This relationship is illustrated in FIG. 3, which shows in greater detail how the output current and output voltage of the transistor 12 vary during the time period when the amplifier is turning off and blocking the resonant voltage swing, i.e., during intervals 56, 59, and 60 of FIG. 2. Compared to FIG. 2, the voltage scale for in FIG. 3 is not enlarged. Thus, the small V.sub.ce values (e.g., V.sub.fl and V.sub.fl) which occur during intervals 52 and 56 cannot be distinguished in FIG. 3.
An important factor in minimizing the transient power dissipation is adjusting amplifier input current I.sub.bf (i.e., current 50 in FIG. 1 and the upper trace in FIG. 2) during the interval 52 so as to provide adequate drive current to turn the transistor 12 on during the interval 52 while minimizing the stored charge that must be later removed during the interval 56 by the current 54. In FIG. 4, the I.sub.c trace 70 and the V.sub.ce trace 72 correspond to the I.sub.c and V.sub.ce traces shown in FIG. 2 when the circuit 10 is adjusted to provide minimum transient power dissipation. FIG. 3 shows how the I.sub.c and V.sub.ce traces are affected by increasing and decreasing the amount of I.sub.bf during the interval 52. Increasing I.sub.bf has the effect of extending the falling portion of the I.sub.c trace 70 to the right in the direction of arrow 74 to location 70', i.e., toward a later time. Decreasing L.sub.bf has the effect of extending the rising portion of the V.sub.ce trace 72 to the left in the direction of arrow 76 to location 72', i.e., toward an earlier time. Having I.sub.c fall more gradually or V.sub.ce rise more gradually increase the I.sub.c V.sub.ce transient product and increases the switching power dissipation.
The foregoing drive circuit is described in greater detail in U.S. Pat. No. 5,107,190, incorporated herein by reference.
The circuit of FIG. 1 produces a ramp of base drive current, eliminating the heavy overdrive at the beginning of the collector current ramp and avoiding under drive just prior before turning the device off. A significant problem with this arrangement, however, is that the base current I.sub.bf changes with changes in frequency. As a result, the ratio I.sub.c /I.sub.bf is also frequency dependent. FIG. 4 and FIG. 5 illustrate in approximate terms the base drive current of the circuit of FIG. 1 at scan frequencies of 30 kHz and 80 kHz, respectively. In order to control the switch transistor 12 efficiently, a constant ratio I.sub.c /I.sub.bf is required.
One possible solution would be to vary the DC supply for the base drive. This approach suffers from numerous disadvantages including increased component count, increased cost, the need to control the DC supply, and power-losses. Hence, generating a frequency independent base current using the foregoing design would necessitate higher cost and higher power losses.
As may be appreciated from the foregoing discussion, designing a suitable drive circuit for the scan output stage involves a number of subtle complexities. When separate scan and EHT output stages are provided, devising an economical way to efficiently drive both output stages become problematic.